It is generally desirable that transistors in integrated circuits generate constant, predictable currents even with changing temperatures. Without any temperature compensation circuitry, the current through a bipolar transistor increases due to the increasing beta of the transistor with temperature.
In relatively high-current applications, it is common to connect a number of transistors in parallel, whereby each transistor contributes a portion of the total current. In this parallel configuration, each transistor is generally designed to be identical and is designed to generate its allocated current at a specified operating temperature. However, if one of these transistors connected in parallel were to become hotter than the other transistors, this hotter transistor would draw more current than the other transistors. This increased current would raise the temperature of that transistor, which would then additionally raise the current through that transistor, and thus raise the temperature even higher. This thermal runaway continues until the transistor is destroyed by the heat overload.
In an attempt to prevent this thermal runaway from happening, ballast resistors are sometimes used as shown in FIG. 1a.
FIG. 1a illustrates a number of identical NPN bipolar transistors being connected in parallel. Only transistors Q1 and Q2 are shown for simplicity. The transistors Q1 and Q2 are shown with a base ballast resistor R1 connected to the base metal 10, so that a transistor's base current flows through its base ballast resistor R1. An emitter ballast resistor R2 is shown connecting the emitters of transistors Q1 and Q2 to the emitter metal 12, so that a transistor's emitter current flows through its emitter ballast resistor R2.
FIGS. 1b, 1c, and 1d are cross-sectional views of known embodiments of transistor Q1 or Q2 incorporating a base ballast resistor or an emitter ballast resistor.
FIG. 1b illustrates a transistor having an inherent base ballast resistor R1. Base metal 10 and emitter metal 12 are connected to the base region 14 (through base pick-up region 20) and the emitter region 16, respectively. Typically, the base ballast resistor R1 is a small value and is formed by the intrinsic resistance of the base P-well 14 in which the N-type emitters 16 are formed. Also shown in FIG. 1b is an N-epitaxial/collector layer 22, an N+ buried collector region 24, and a P- substrate 28.
The intrinsic base ballast resistor R1 works as follows. An increased temperature of transistor Q1 results in an increased emitter current (I.sub.E) through transistor Q1 and a lowering of the transistor's base-emitter voltage (V.sub.BE). This draws an additional base current (I.sub.B) through the base ballast resistor R1 and slightly lowers the base voltage applied to transistor Q1. This reduced V.sub.BE causes transistor Q1 to be less conductive so as to partially counteract the increased beta due to the increased temperature. If base ballast resistor R1 were of a sufficient resistance, this resistor R1 would provide adequate temperature compensation circuitry for the transistor. However, using the standard base diffusion as the ballast resistor is not very effective due to the typically low resistance (e.g., 100-200 ohms/square) of the standard base diffusion and the very small change in base current with respect to emitter current.
A much more efficient way to provide this temperature compensation of transistors Q1 and Q2 is using an emitter ballast resistor R2, shown in FIGS. 1c and 1d. An increased current through resistor R2 will lower the emitter voltage of transistor Q1 or Q2 and hence lower the V.sub.BE. Since any increase in emitter current through transistor Q1 or Q2 will be much greater than any increase in the base current, only a relatively small emitter ballast resistor R2 need be used to dramatically lower the V.sub.BE of the transistor when emitter current is increased due to an increased temperature of transistor Q1 or Q2.
One popular form of emitter ballast resistor R2 is shown in FIG. 1c and is implemented using an N+ diffusion resistor 30 as an emitter series resistor. Metal 12 contacts one end of the emitter series resistor 30, and a metal connector 32 connects the other end of resistor 30 to the emitter region 16.
Another popular form of emitter ballast resistor R2 is a separate, extrinsic polysilicon resistor 34, shown in FIG. 1d, where each polysilicon resistor 34 is connected between the emitter metal 12 and an emitter region 16 of a transistor using a metal connector 36.
In the prior art, such as shown in FIGS. 1b, 1c, and 1d, the standard base diffusion for the NPN transistor has a typical resistivity of 100-200 ohms/square. The standard base diffusion is fairly shallow, on the order of 3 microns deep. This high doping level of the standard base diffusion enables the standard base diffusion to contain the relatively large amount of charge required to avoid punch-through breakdown of the transistor at the operating voltage.
A number of drawbacks exist with the prior art structures of FIGS. 1b, 1c, 1d, and similar structures. One drawback is that the intrinsic base ballast resistor R1 formed by the resistivity of the standard base diffusion is small and has relatively little effect on the temperature/current compensation of the resulting transistor. Additionally, the intrinsic pinch resistor in the shallow standard base diffusion under emitter 16 is a relatively high resistance and, during the turn-off transient, the dV/dt current through the base/collector parasitic capacitor 38 causes a voltage drop across the pinch resistor which may effectively keep the transistor turned on even after the transistor was intended to be turned off. Additionally, when the transistor is on, the high value pinch resistor in the base diffusion under the emitter region 16 prevents the portion of the transistor under the emitter region 16 farthest from the base contact from turning fully on.
Further, since the base ballast resistor R1 is of a low value, the emitter ballast resistor R2 must be made a relatively high value to obtain the necessary temperature compensation for the transistor. This high-value emitter ballast resistor R2 undesirably causes the output saturation voltage of the transistor to be higher.
Still further, the emitter ballast resistors require a large amount of silicon real estate solely dedicated to these resistors, and the values of these resistors are directly affected by mask alignments.
Accordingly, the prior art transistors and ballast resistors have significant operational drawbacks and size drawbacks.
It is therefore desirable in the field of high power transistor integrated circuits to form more efficient emitter and base ballast resistors. It is also desirable to form transistors in parallel for high current applications, where each transistor exhibits identical characteristics when in an operational environment so that each transistor will conduct a same amount of current. It is also desirable to form these transistors using a minimum of process steps and a minimum of die area.